From the beginning of analog integrated circuit design around 1960 up to present the operational amplifier (op-amp)has been the most important analog building block. The operational transconductance amplifier (OTA) as stand-alone circuit has been introduced with the development of switched-capacitor circuits in the early 1980s. For the ideal OTA the differential input voltage steers the output current and so the transfer function of an OTA stage is defined by its transconductance and the output load. OTAs are stabilized by their load and the OTA power consumption can be optimized for the load, whereas op-amps need internal compensation for stabilization to approach load independent behavior. Because the OTAs are not subject to prior performance loss due to internal compensation they can achieve superior performance with high impedance environments, such as switched capacitor sampled-data circuits.
High output impedance is an important OTA requirement for many practical applications. The regulated cascode technique supports this requirement very well. By creation of an inner feedback loop with another amplification stage the OTAs DC-gain and thereby the output impedance can be boosted to nearly ideal level without compromising the frequency response. With this technique the trade-off between DC-gain and speed in amplifier design can be resolved. While the regulating amplifier delivers the required additional DC-gain, the main amplifier can be optimized for speed at a given power or, vice versa, for power at a given speed. The optimization of the main cascode amplifier can be formulated analytically for open as well as for closed-loop configuration. The solution must in general be found by numerical evaluation because of the complexity in modeling the MOS transistor devices with acceptable accuracy. This optimization has been performed for folded and telescopic cascode amplifier topologies and the results are discussed with respect to phase margin, output swing, capacitive load, topology and technology dependence. For closed-loop configuration the amplifier speed can be even increased beyond the level of an ideal OTA. The optimization method is proven by a series of implemented amplifiers spanning a bias range from 1 µ A to 10 mA. The regulating amplifier should add the required DC-gain in a power-efficient way without deterioration of the amplifier's frequency response and settling behavior. It adds a pole-zero pair to the amplifiers transfer function which can be well controlled by the regulating amplifier's compensation capacitance. This leads to a method for power efficient design with good settling performance.
The Delta Sigma technique trades resolution with speed in converter design. With high enough oversampling the quantization noise can be rendered arbitrarily low. A Delta Sigma modulator's performance is therefore usually limited by circuit thermal noise where the first stage contributes most. Today, the practical design for single-loop, single-bit modulators follows well established paths. However, the optimization of power consumption which is a key requirement for battery operated devices is still an open subject. The latter is addressed in this thesis throughout the whole design flow. At architecture level a careful balance between quantization and circuit thermal noise is needed. For an SC implementation at circuit level, capacitances and bias currents are scaled according to the relative importance of noise contribution. Behavioral level simulations modeling the essential integrator characteristics help to find tight specifications for the building blocks. Closed-loop amplifier optimization provides the link to component level design. A power estimation formula allows different design decisions to be compared. The design concepts have been proven with a baseband modulator for GSM application and an IF input modulator for dual UMTS/GSM application.

Series in Microelectronics

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