Series in Microelectronics

edited by Wolfgang Fichtner
Qiuting Huang
Heinz Jäckel
Hans Melchior
George S. Moschytz
Gerhard Tröster

Vol. 143

Rolf Enzler,
Architectural Trade-offs in Dynamically Reconfigurable Processors.
2004; 170 pages. 64,00. ISBN 3-89649-919-X

Reconfigurable computing systems are an emerging class of adaptive computing platforms. Their key feature is the ability to perform computations in hardware to increase performance, while retaining the flexibility of software-based solutions. This work deals with the design and evaluation of dynamically reconfigurable processors that couple a standard CPU core with a reconfigurable processing unit. To study the design decisions and architectural trade-offs involved, an evaluation methodology is proposed that allows architectural features to be investigated at the system level. A reconfigurable processor architecture targeting the embedded systems domain is presented and evaluated. The architecture incorporates a coarse-grained, multi-context reconfigurable array tailored for data-streaming multimedia applications.

About the author:

Rolf Enzler received the Dipl.-Ing. (MSc) and Dr. sc. techn. (PhD) degrees in information technology and electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 1997 and 2004, respectively. He joined the Electronics Laboratory at ETH Zurich in 1997 as a research and teaching assistant in the Computer Architecture Group. His research interests include reconfigurable computing, hardware/software codesign, embedded systems, and application-specific computing architectures.

Keywords:
Reconfigurable Computing, Application-Specific Computing Architectures, Field-Programmable Gate Arrays (FPGAs), Reconfigurable Processors, Run-Time Reconfiguration, Embedded Systems, Hardware/Software Codesign, Workload Characterization, Co-simulation, Performance Modeling

Series in Microelectronics

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