Series in Microelectronics
Preserving High Resolution in
CMOS Pipelined A/D Converters
2010. 262 pages. ISBN 3-86628-316-4 and 978-3-86628-316-9
While the continuing development of new process technologies with shrinking minimum feature sizes allows digital designs to have higher integration densities and more functionality per area, analog circuits increasingly suffer from the lowering of the supply voltage. The design of analog-to-digital converters (ADCs) is particularly affected by this problem. This thesis focuses on achieving high resolutions in pipelined ADCs running at low supply voltages. After an introduction comprising an overview of converter architectures and a literature summary, noise and error sources in pipelined converters are analyzed. Architectural considerations with a special focus on removing the dedicated sample-and-hold stage present in most published designs follow, and different calibration schemes for certain subcircuits are described as well. Two chapters deal with the implementation and measurements of realized converters, together with an analysis of encountered problems.
About the Author
Jürg Treichler received the Dipl. Ing. ETH degree in Electrical Engineering from ETH Zurich in 2003. He joined the Integrated Systems Laboratory (IIS) of ETH in the same year as a research and teaching assistant, where he worked on the design of analog and mixed-signal integrated circuits with a focus on pipelined A/D converters.
Keywords: Keywords: data converters, pipelined, A/D converters, ADC, CMOS, analog circuits, IC design, switched-capacitor, calibration.
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