Series in Microelectronics
edited by
Wolfgang Fichtner
Qiuting Huang
Heinz Jäckel
Gerhard Tröster
Bernd Witzigmann
Christian Benkeser,
Power Efficiency and the
Mapping
of Communication Algorithms into VLSI
2010. XII, 178 pages. € 64,00.
ISBN 3-86628-323-7 and 978-3-86628-323-7
Abstract:
To satisfy the growing demands of today’s information society, hardware
solutions have to process complex algorithms at high data rates. The key enabler
for the required computational power has been the great and continuous progress
in CMOS technology. However, in digital circuits implemented in recent deep
submicron CMOS technologies power consumption has become a major bottleneck.
This work explores the
potential of improving the power efficiency of digital circuits using
optimizations at the algorithmic and architectural level. To this end, the
impact of the algorithm characteristics on architectural complexity is
investigated and high-level, low-power design techniques are discussed. To
demonstrate the effectiveness of the proposed methods power-efficient ASIC
implementations solving the major challenges of the digital baseband in 2G, 3G
and 4G cellular systems have been realized, with a focus on turbo decoding and
channel equalization.
About the Author
Christian Benkeser was born
in Bühl/Baden, Germany, in 1977. He received his M.S. degree in Electronical
Engineering from the University of Karlsruhe (TH), Germany, in 2004. In the
same year, he joined the Integrated Systems Laboratory (IIS) of the Swiss
Federal Institute of Technology (ETH) Zurich where he worked as a research and
teaching assistant in the area of circuits and systems for wireless
communications. In 2009, he was awarded the Dr. Sc. (Ph. D.) degree by the ETH
Zurich.
Short TOC
Contents
1 Introduction
1.1 Recent Trends in Mobile
Communications
1.2 Contributions
1.3 Outline of the Thesis
2 Design Space Exploration
2.1 Terminology
2.2 High-level criteria for complexity
2.3 Implementation-related Algorithm Characteristics
2.4 Metrics for comparing Architecture Complexity
2.5 Evaluation of Hardware Platforms
2.6 Digital Design for Low Power
2.7 Summary
3 Turbo Decoder Design and Optimization
3.1 Turbo Coding
3.2 High-Level Architecture Exploration
3.3 Optimized SISO Decoder Design
3.4 Implementation of a 3GPP Interleaver
3.5 Turbo Decoder Implementations
3.6 Summary
4 Digital Receiver Design for the GSM Evolution
4.1 System Overview
4.2 Equalizer Concepts for EGPRS
4.3 Exploration of Channel Equalization
4.4 Low-Complexity Pre-filter
4.5 Efficient DDFSE Implementation
4.6 VLSI Implementations and Comparison
4.7 Summary
5 Summary and Conclusion
A Chip photos
B GSM Test Channels
C GSM Pulses
Acronyms
Bibliography
Keywords: low-power, IC design, CMOS, receiver,
wireless, communication, baseband, turbo decoder, equalizer.
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