Hartung-Gorre Verlag
Inh.: Dr.
Renate Gorre D-78465
Konstanz Fon: +49 (0)7533 97227 Fax: +49 (0)7533 97228 www.hartung-gorre.de
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Series in
Microelectronics
edited by
Luca Benini,
Qiuting
Huang,
Taekwang Jang,
Mathieu
Luisier,
Christoph
Studer,
Hua Wang
Andreas
Dominic Kurth
An Open-Source Research
Platform for Heterogeneous
Systems on Chip
1st Edition 2022. XVI, 264 pages. € 64,00.
ISBN 978-3-86628-774-7
Abstract:
Heterogeneous systems on chip (HeSoCs)
combine general-purpose, feature-rich multi-core host processors with
domain-specific programmable many-core accelerators (PMCAs) to unite
versatility with energy efficiency and peak performance. By virtue of their
heterogeneity, HeSoCs hold the promise of increasing
performance and energy efficiency compared to homogeneous multiprocessors,
because applications can be executed on hardware that is designed for them.
However, this heterogeneity also increases system complexity substantially.
This thesis presents the first research platform for HeSoCs where all components, from accelerator cores to
application programming interface, are available under permissive open-source
licenses. We begin by identifying the hardware and software components that are
required in HeSoCs and by designing a representative
hardware and software architecture. We then design, implement, and evaluate
four critical HeSoC components that have not been
discussed in research at the level required for an open-source implementation:
First, we present a modular, topology-agnostic, high-performance on-chip
communication platform, which adheres to a state-of-the-art industry-standard
protocol. We show that the platform can be used to build high-bandwidth (e.g.,
2.5 GHz and 1024 bit data width) end-to-end communication fabrics with high
degrees of concurrency (e.g., up to 256 independent concurrent transactions).
Second, we present a modular and efficient solution for implementing atomic
memory operations in highly-scalable many-core processors, which demonstrates
near-optimal linear throughput scaling for various synthetic and real-world
workloads and requires only 0.5 kGE per core. Third,
we present a hardware-software solution for shared virtual memory that avoids
the majority of translation lookaside buffer misses with prefetching, supports
parallel burst transfers without additional buffers, and can be scaled with the
workload and number of parallel processors. Our work improves accelerator
performance for memory-intensive kernels by up to 4×. Fourth, we present a
software toolchain for mixed-data-model heterogeneous compilation and OpenMP offloading. Our work enables transparent memory
sharing between a 64-bit host processor and a 32-bit accelerator at overheads
below 0.7 % compared to 32-bit-only execution. Finally, we combine our
contributions to a research platform for state-of-the-art HeSoCs
and demonstrate its performance and flexibility in multiple case studies.
Keywords: Heterogeneous (Hybrid)
Computing Systems, Parallel Processors, Shared Memory, On-Chip Networks,
Hardware/Software Interfaces, System Architectures
About the Author:
Andreas Kurth was born in
Switzerland in 1990. He received his MSc degree in electrical engineering and
information technology from ETH Zurich in 2017. He then joined the group of
Prof. Dr. Luca Benini at the Integrated Systems
Laboratory (IIS) at ETH Zurich. His research interests include the architecture
and programming of heterogeneous systems on chip (SoCs)
and accelerator-rich computing systems.
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